1. Field of the Invention
This disclosure relates to a semiconductor device and, more particularly, to a MOS (metal-oxide-semiconductor) transistor having a recessed gate electrode and a fabrication method thereof.
2. Description of Related Art
Semiconductor devices comprise an integrated circuit composed of a plurality of discrete devices such as transistors. The transistors can be typically categorized as either MOS transistors or bipolar transistors. MOS transistors have various advantages over bipolar transistors. For instance, MOS transistors consume less power and have greater integration density characteristics as compared to bipolar transistors. Accordingly, MOS transistors are employed in the majority of semiconductor devices.
Recently, a MOS transistor having a recessed gate electrode has been proposed in order to increase the integration density of the semiconductor device. A fabrication method of the MOS transistor having the recessed gate electrode is taught in U.S. Pat. No. 6,358,800 to Tseng, entitled “method of forming a MOSFET with a recessed-gate having a channel length beyond photolithography limit”.
FIG. 1 is a cross sectional view illustrating a MOS transistor disclosed in the U.S. Pat. No. 6,358,800.
Referring to FIG. 1, an isolation layer 112 is formed at a predetermined region of a semiconductor substrate 110, thereby defining an active region. A first insulating layer 114 and a second insulating layer (not shown) are sequentially formed on the entire surface of the substrate having the active region. The second insulating layer is patterned to a first opening over the active region. A third insulating layer is formed on the entire surface of the substrate including the first opening. The third and first insulating layers are then anisotropically etched to form a first oxide spacer 122 on the sidewall of the first opening and to simultaneously form a second opening that exposes a predetermined region of the active region, e.g., the semiconductor substrate (110).
The exposed semiconductor substrate is selectively etched to form a trench region. A second oxide spacer 128 is then formed on the sidewalls of the first oxide spacer 122 and the trench region. The second oxide spacer 128 contains dopants therein. A gate insulating layer 130 is formed on the bottom surface of the trench region. A gate electrode 132A, which fills the trench region, is formed on the gate insulating layer 130. The second insulating layer is removed to expose the first insulating layer 114. Impurity ions are implanted into the active region using the gate electrode 132A as an ion implantation mask. As a result, source/drain regions 136 are formed on both sides of the gate electrode 132A.
The substrate having the source/drain regions 136 is annealed to out-diffuse the dopants in the second oxide spacer 128. Thus, source/drain extensions 138 are formed at the sidewall of the trench region that is in contact with the second oxide spacer 128. Subsequently, a third spacer 140 is formed on the sidewall of the first oxide spacer 122. Finally, metal contacts 142 and 144 are selectively formed on the gate electrode 132A and the source/drain regions 136, respectively.
According to the foregoing prior art, it is possible to form a MOS transistor having a channel length shorter than the resolution limit of a photolithography process by using the first and second spacers 122 and 128. However, the source/drain extensions 138 are formed by the out-diffusion of the dopants contained in the second spacer 128. Accordingly, whenever a subsequent annealing process is performed, the dopants in the second spacer 128 may be further supplied into the source/drain extensions 138. As a result, the subsequent annealing process may cause the junction depth and width of the source/drain extensions 138 to increase, as well as the effective channel length (L of FIG. 1), corresponding to the distance between the source/drain extensions 138, to decrease. This is because the dopants in the source/drain extensions 138 can diffuse along a horizontal direction and a vertical direction. Thus, it is difficult to precisely control the junction depth of the source/drain extensions 138, as well as control the effective channel length L.
The source/drain extensions 138 correspond to an LDD (lightly doped drain) region of a conventional planar-type MOS transistor. The concentration of the dopants and the junction depth of the LDD region directly affect performance characteristics of the MOS transistor, such as drain breakdown voltage, hot carrier effect and short channel effect. However, according to the foregoing prior art, it is difficult to accurately control the concentration of the dopants in the source/drain extensions 138.
Further, the channel length is directly related to the width of the trench region. In other words, even if the depth of the trench region is increased, the channel length will not be changed. Therefore, the width of the trench region would have to be increased in order to form a MOS transistor having a long channel. As a result, even though semiconductor devices are fabricated using the above-mentioned prior art, it is difficult to obtain the same high integration density as semiconductor devices employing the conventional planar-type MOS transistors.
Embodiments of the invention address these and other deficiencies in the prior art.